FIG. 1 shows a block diagram of a portion of a conventional SOC 100, such as a digital signal processor (DSP) or microprocessor. As shown, the SOC includes a processor 110 coupled to a memory module 112 via a plurality of data, address and control lines. The memory module stores a computer program comprising a sequence of instructions. During operation, the processor selects one of the memory units through its address bus 120. The program instructions from memory are retrieved via data bus 122 to perform the desired function. Data, variable parameters and intermediate results may be transferred to and from the memory units or peripheral units selected by the address bus 126, via data bus 128. Control information is transferred through a plurality of control lines 134.
Once the processor sends an address on the address bus, it expects a response within a given time interval. If the processor communicates with a slow memory or peripheral, the access time may be longer than the allowable timing requirement. The processor typically enters a wait-state to allow the memory or peripheral sufficient time to complete the operation requested by the processor. Wait states may also be inserted in other situations, such as during memory refresh operations or shared memory bus arbitration.
FIG. 2 shows the timing diagram for the data transfers according to the SOC 100. When a wait signal (WS) is issued, the processor suspends execution for the next few cycles until the wait signal is deactivated. Alternatively, an unmasked interrupt may be issued to terminate the wait state in some processors. The wait states are used to provide sufficient time for the data PD(Ax) and DD(Ax) to be available on the data buses when the addresses PA(x) and DA(x) are placed on the address buses.
The wait signal has to be ready before the wait signal setup time tWS to allow sufficient time for the processor to respond to the wait signal. However, tWS is very difficult to satisfy especially if it is high, since some processing time is typically required to issue the wait signal. If tWS is not met, as shown in FIG. 3, the next addresses PA(y) and DA(y) will be placed on the address buses before the previous data PD(Ax) and DD(Ax) is ready to be accessed from the data buses. Corrupted data may be accessed by the processor, causing system failure and loss of data integrity.
As evidenced from the above discussion, it is desirable to provide an improved SOC architecture.